I. Mrozek ; N. A. Shevchenko ; V. N. Yarmolik - Universal Address Sequence Generator for Memory Built-in Self-test

fi:10000 - Fundamenta Informaticae, January 10, 2023, Volume 188, Issue 1
Universal Address Sequence Generator for Memory Built-in Self-test

Authors: I. Mrozek ; N. A. Shevchenko ; V. N. Yarmolik

    This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, $2^i$, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.


    Volume: Volume 188, Issue 1
    Published on: January 10, 2023
    Accepted on: September 5, 2022
    Submitted on: September 5, 2022
    Keywords: Computer Science - Hardware Architecture

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